Sciweavers

DATE
2008
IEEE
138views Hardware» more  DATE 2008»
13 years 11 months ago
Dynamic Task Allocation Strategies in MPSoC for Soft Real-time Applications
This work evaluates task allocation strategies based on bin-packing algorithms in the context of multiprocessor systems-on-chip (MPSoCs) with task migration capabilities, running ...
Eduardo Wenzel Brião, Daniel Barcelos, Fl&a...
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
13 years 11 months ago
Synthesis of Fault-Tolerant Embedded Systems
This work addresses the issue of design optimization for faulttolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpoin...
Petru Eles, Viacheslav Izosimov, Paul Pop, Zebo Pe...
DATE
2008
IEEE
115views Hardware» more  DATE 2008»
13 years 11 months ago
Synthesizing Synchronous Elastic Flow Networks
This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...
Greg Hoover, Forrest Brewer
DATE
2008
IEEE
127views Hardware» more  DATE 2008»
13 years 11 months ago
An application-based EDF scheduler for OSEK/VDX
Claas Diederichs, Ulrich Margull, Frank Slomka, Ge...
DATE
2008
IEEE
223views Hardware» more  DATE 2008»
13 years 11 months ago
Cooperative Safety: a Combination of Multiple Technologies
—Governmental Transportation Authorities' interest in Car to Car and Car to Infrastructure has grown dramatically over the last few years in order to increase the road safet...
Raffaele Penazzi, Piergiorgio Capozio, Martin Dunc...
DATE
2008
IEEE
78views Hardware» more  DATE 2008»
13 years 11 months ago
Simultaneous FU and Register Binding Based on Network Flow Method
– With the rapid increase of design complexity and the decrease of device features in nano-scale technologies, interconnection optimization in digital systems becomes more and mo...
Jason Cong, Junjuan Xu
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
13 years 11 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie
DATE
2008
IEEE
84views Hardware» more  DATE 2008»
13 years 11 months ago
On the Verification of High-Order Constraint Compliance in IC Design
Jan B. Freuer, Göran Jerke, Joachim Gerlach, ...
DATE
2008
IEEE
90views Hardware» more  DATE 2008»
13 years 11 months ago
Computation of Buffer Capacities for Throughput Constrained and Data Dependent Inter-Task Communication
Abstract - Streaming applications are often implemented as task graphs. Currently, techniques exist to derive buffer capacities that guarantee satisfaction of a throughput constrai...
Maarten Wiggers, Marco Bekooij, Gerard J. M. Smit