DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have b...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
Early evaluation allows to execute operations when enough information at the inputs has been received to determine the value at the outputs. Systems that can tolerate variable-lat...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
A protocol for latency-insensitive design with early evaluation is presented. The protocol is based on a symmetric view of the system in which tokens carrying information move in ...