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ASPDAC
2008
ACM
91views Hardware» more  ASPDAC 2008»
13 years 6 months ago
Heuristic power/ground network and floorplan co-design method
It's a trend to consider power supply integrity at early stage to improve the design quality. In this paper, we propose a novel algorithm to optimize floorplan together with P...
Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong
ICCAD
2000
IEEE
94views Hardware» more  ICCAD 2000»
13 years 9 months ago
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan
––In this paper, a corner block list — a new efficient topological representation for non-slicing floorplan is proposed with applications to VLSI floorplan and building block...
Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu,...
ASPDAC
2006
ACM
120views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Design space exploration for minimizing multi-project wafer production cost
- Chip floorplan in a reticle for Multi-Project Wafer (MPW) plays a key role in deciding chip fabrication cost. In this paper1 , we propose a methodology to explore reticle floopla...
Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-...