Sciweavers

FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
13 years 8 months ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
FPGA
2000
ACM
128views FPGA» more  FPGA 2000»
13 years 8 months ago
Factoring large numbers with programmable hardware
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
Hea Joung Kim, William H. Mangione-Smith
FPGA
2000
ACM
175views FPGA» more  FPGA 2000»
13 years 8 months ago
An FPGA implementation and performance evaluation of the Serpent block cipher
With the expiration of the Data Encryption Standard (DES) in 1998, the Advanced Encryption Standard (AES) development process is well underway. It is hoped that the result of the ...
Adam J. Elbirt, Christof Paar
FPGA
2000
ACM
177views FPGA» more  FPGA 2000»
13 years 8 months ago
Automatic generation of FPGA routing architectures from high-level descriptions
In this paper we present a "high-level" FPGA architecture description language which lets FPGA architects succinctly and quickly describe an FPGA routing architecture. W...
Vaughn Betz, Jonathan Rose
FPGA
2000
ACM
114views FPGA» more  FPGA 2000»
13 years 8 months ago
Synthesis for FPGAs with embedded memory blocks
Jason Cong, Kenneth Yan
FPGA
2000
ACM
125views FPGA» more  FPGA 2000»
13 years 8 months ago
Technology mapping for k/m-macrocell based FPGAs
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...
Jason Cong, Hui Huang, Xin Yuan
FPGA
2000
ACM
161views FPGA» more  FPGA 2000»
13 years 8 months ago
The effect of LUT and cluster size on deep-submicron FPGA performance and density
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
Elias Ahmed, Jonathan Rose