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FPGA
2000
ACM
109views FPGA» more  FPGA 2000»
10 years 7 months ago
Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays
It has become clear that on-chip storage is an essential component of high-density FPGAs. These arrays were originally intended to implement storage, but recent work has shown tha...
Steven J. E. Wilton
FPGA
2000
ACM
145views FPGA» more  FPGA 2000»
10 years 7 months ago
A C compiler for a processor with a reconfigurable functional unit
This paper describes a C compiler for a mixed Processor/FPGA architecture where the FPGA is a Reconfigurable Functional Unit (RFU). It presents three compilation techniques that c...
Zhi Alex Ye, U. Nagaraj Shenoy, Prithviraj Banerje...
FPGA
2000
ACM
120views FPGA» more  FPGA 2000»
10 years 7 months ago
A novel high throughput reconfigurable FPGA architecture
With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial...
Amit Singh, Luca Macchiarulo, Arindam Mukherjee, M...
FPGA
2000
ACM
479views FPGA» more  FPGA 2000»
10 years 7 months ago
Implementing a RAKE receiver for wireless communications on an FPGA-based computer system
RAKE receivers are widely used in the wireless communications industry. Currently, custom VLSI is the most popular implementation. Programmable and reconfigurable logic implementa...
Ali M. Shankiti, Miriam Leeser
FPGA
2000
ACM
119views FPGA» more  FPGA 2000»
10 years 7 months ago
Timing-driven placement for FPGAs
In this paper we introduce a new Simulated Annealingbased timing-driven placement algorithm for FPGAs. This paper has three main contributions. First, our algorithm employs a nove...
Alexander Marquardt, Vaughn Betz, Jonathan Rose
FPGA
2000
ACM
98views FPGA» more  FPGA 2000»
10 years 7 months ago
Field programmable port extender (FPX) for distributed routing and queuing
John W. Lockwood, Jonathan S. Turner, David E. Tay...
FPGA
2000
ACM
114views FPGA» more  FPGA 2000»
10 years 7 months ago
Generating highly-routable sparse crossbars for PLDs
A method for evaluating and constructing sparse crossbars which are both area efficient and highly routable is presented. The evaluation method uses a network flow algorithm to ac...
Guy G. Lemieux, Paul Leventis, David M. Lewis
FPGA
2000
ACM
150views FPGA» more  FPGA 2000»
10 years 7 months ago
Programmable memory blocks supporting content-addressable memory
The Embedded System Block (ESB) of the APEX E programmable logic device family from Altera Corporation includes the capability of implementing content addressable memory (CAM) as ...
Frank Heile, Andrew Leaver, Kerry Veenstra
FPGA
2000
ACM
141views FPGA» more  FPGA 2000»
10 years 7 months ago
Tolerating operational faults in cluster-based FPGAs
In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain ...
Vijay Lakamraju, Russell Tessier
FPGA
2000
ACM
168views FPGA» more  FPGA 2000»
10 years 7 months ago
A benchmark suite for evaluating configurable computing systems--status, reflections, and future directions
This paper presents a benchmark suite for evaluating a configurable computing system's infrastructure, both tools and architecture. A novel aspect of this work is the use of ...
S. Kumar, Luiz Pires, Subburajan Ponnuswamy, C. Na...
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