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    FPL
    2009
    Springer
    166views Hardware» more  FPL 2009»
    Modeling post-techmapping and post-clustering FPGA circuit depth
    13 years 9 months ago
    Modeling post-techmapping and post-clustering FPGA circuit depth
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    This paper presents an analytical model that relates FPGA architectural parameters to the expected speed of FPGA implementation. More precisely, the model relates the lookuptable ...
    Joydip Das, Steven J. E. Wilton, Philip Heng Wai L...
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