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    FPGA
    2008
    ACM
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    FPGA interconnect design using logical effort
    13 years 6 months ago
    FPGA interconnect design using logical effort
    Download  www.cse.cuhk.edu.hk
    Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
    Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong
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