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TVLSI
2008
123views more  TVLSI 2008»
10 years 4 months ago
Cost-Efficient SHA Hardware Accelerators
Abstract--This paper presents a new set of techniques for hardware implementations of Secure Hash Algorithm (SHA) hash functions. These techniques consist mostly in operation resch...
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Sta...
SCN
2008
Springer
10 years 4 months ago
Using Normal Bases for Compact Hardware Implementations of the AES S-Box
Abstract. The substitution box (S-box) of the Advanced Encryption Standard (AES) is based on the multiplicative inversion s(x) = x-1 in GF(256) and followed by an affine transforma...
Svetla Nikova, Vincent Rijmen, Martin Schläff...
CSREASAM
2009
10 years 5 months ago
Tantra: A Fast PRNG Algorithm and its Implementation
Tantra 1 is a novel Pseudorandom number generator (PRNG) design that provides a long sequence high quality pseudorandom numbers at very high rate both in software and hardware impl...
Mahadevan Gomathisankaran, Ruby Lee
HPCA
1995
IEEE
10 years 7 months ago
Implementation of Atomic Primitives on Distributed Shared Memory Multiprocessors
In this paper we consider several hardware implementations of the general-purpose atomic primitives fetch and Φ, compare and swap, load linked, and store conditionalon large-scal...
Maged M. Michael, Michael L. Scott
FDTC
2006
Springer
74views Cryptology» more  FDTC 2006»
10 years 7 months ago
Fault Attack Resistant Cryptographic Hardware with Uniform Error Detection
Traditional hardware error detection methods based on linear codes make assumptions about the typical or expected errors and faults and concentrate the detection power towards the ...
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander...
FSE
2004
Springer
123views Cryptology» more  FSE 2004»
10 years 8 months ago
ICEBERG : An Involutional Cipher Efficient for Block Encryption in Reconfigurable Hardware
Abstract. We present a fast involutional block cipher optimized for reconfigurable hardware implementations. ICEBERG uses 64-bit text blocks and 128-bit keys. All components are in...
François-Xavier Standaert, Gilles Piret, Ga...
CHES
2006
Springer
246views Cryptology» more  CHES 2006»
10 years 8 months ago
Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations
This article starts with a discussion of three different attacks on masked AES hardware implementations. This discussion leads to the conclusion that glitches in masked circuits po...
Stefan Mangard, Kai Schramm
CHES
2004
Springer
106views Cryptology» more  CHES 2004»
10 years 8 months ago
XTR Implementation on Reconfigurable Hardware
Abstract. Recently, Lenstra and Verheul proposed an efficient cryptosystem called XTR. This system represents elements of F p6 with order dividing p2 -p+1 by their trace over Fp2 ....
Eric Peeters, Michael Neve, Mathieu Ciet
CHES
1999
Springer
91views Cryptology» more  CHES 1999»
10 years 8 months ago
A High-Performance Flexible Architecture for Cryptography
Cryptographic algorithms are more efficiently implemented in custom hardware than in software running on general-purpose processors. However, systems which use hardware implementat...
R. Reed Taylor, Seth Copen Goldstein
FPL
2003
Springer
114views Hardware» more  FPL 2003»
10 years 9 months ago
Power Analysis of FPGAs: How Practical is the Attack?
Recent developments in information technologies made the secure transmission of digital data a critical design point. Large data flows have to be exchanged securely and involve en...
François-Xavier Standaert, Loïc van Ol...
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