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DAC
2011
ACM
12 years 9 months ago
Enabling system-level modeling of variation-induced faults in networks-on-chips
Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However,...
Konstantinos Aisopos, Chia-Hsin Owen Chen, Li-Shiu...
SOCA
2010
IEEE
13 years 7 months ago
Exploiting multicores to optimize business process execution
While modern CPUs offer an increasing number of cores with shared caches, prevailing execution engines for business processes, workflows, or Web service compositions have not been ...
Achille Peternier, Daniele Bonetta, Cesare Pautass...
SIGSOFT
2010
ACM
13 years 7 months ago
Combining hardware and software instrumentation to classify program executions
Several research efforts have studied ways to infer properties of software systems from program spectra gathered from the running systems, usually with software-level instrumentat...
Cemal Yilmaz, Adam A. Porter
EUROPAR
2003
Springer
14 years 2 months ago
Obtaining Hardware Performance Metrics for the BlueGene/L Supercomputer
Hardware performance monitoring is the basis of modern performance analysis tools for application optimization. We are interested in providing such performance analysis tools for t...
Pedro Mindlin, José R. Brunheroto, Luiz De ...
SIGCSE
2010
ACM
164views Education» more  SIGCSE 2010»
14 years 4 months ago
A breadth-first course in multicore and manycore programming
The technique of scaling hardware performance through increasing the number of cores on a chip requires programmers to learn to write parallel code that can exploit this hardware....
Suzanne Rivoire