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CODES
2005
IEEE
10 years 15 days ago
Iterational retiming: maximize iteration-level parallelism for nested loops
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation ...
Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean ...
CODES
2005
IEEE
10 years 15 days ago
Enhanced code density of embedded CISC processors with echo technology
Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even ...
Youfeng Wu, Mauricio Breternitz Jr., Herbert H. J....
CODES
2005
IEEE
10 years 15 days ago
A core flight software system
No two flight missions are alike, hence, development and on-orbit software costs are high. Software portability and adaptability across hardware platforms and operating systems ha...
Jonathan Wilmot
CODES
2005
IEEE
10 years 15 days ago
Retargetable generation of TLM bus interfaces for MP-SoC platforms
In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cor...
Andreas Wieferink, Rainer Leupers, Gerd Ascheid, H...
CODES
2005
IEEE
10 years 15 days ago
Developing design tools for biological and biomedical applications of micro- and nano-technology
This short paper, an update of [75], is intended to provide a brief summary and extensive references on biological applications for micro- and nano-machining, as well as the compu...
Jacob White
CODES
2005
IEEE
10 years 15 days ago
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines
The performance of virtual machines (e.g., Java Virtual Machines—JVMs) can be significantly improved when critical code sections (e.g., Java bytecode methods) are migrated from...
Miljan Vuletic, Christophe Dubach, Laura Pozzi, Pa...
CODES
2005
IEEE
10 years 15 days ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
CODES
2005
IEEE
10 years 15 days ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...
CODES
2005
IEEE
10 years 15 days ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
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