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ICCAD
2000
IEEE
69views Hardware» more  ICCAD 2000»
13 years 9 months ago
Exploring Performance Tradeoffs for Clustered VLIW ASIPs
Margarida F. Jacome, Gustavo de Veciana, Viktor S....
ICCAD
2000
IEEE
77views Hardware» more  ICCAD 2000»
13 years 9 months ago
Improving the Proportion of At-Speed Tests in Scan BIST
A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors ap...
Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janus...
ICCAD
2000
IEEE
91views Hardware» more  ICCAD 2000»
13 years 9 months ago
A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
Jiang Hu, Sachin S. Sapatnekar
ICCAD
2000
IEEE
188views Hardware» more  ICCAD 2000»
13 years 9 months ago
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
Sungpack Hong, Taewhan Kim
ICCAD
2000
IEEE
94views Hardware» more  ICCAD 2000»
13 years 9 months ago
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan
––In this paper, a corner block list — a new efficient topological representation for non-slicing floorplan is proposed with applications to VLSI floorplan and building block...
Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu,...
ICCAD
2000
IEEE
119views Hardware» more  ICCAD 2000»
13 years 9 months ago
Synthesis of Operation-Centric Hardware Descriptions
Most hardware description frameworks, whether schematic or textual, use cooperating finite state machines (CFSM) as the underlying abstraction. In the CFSM framework, a designer ...
James C. Hoe, Arvind
ICCAD
2000
IEEE
137views Hardware» more  ICCAD 2000»
13 years 9 months ago
Smart Simulation Using Collaborative Formal and Simulation Engines
computation and automatic abstraction. Second, Ketchum performs not only automatic test generation but also unreachability analysis, which enables the test generation effort to be ...
Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James ...
ICCAD
2000
IEEE
104views Hardware» more  ICCAD 2000»
13 years 9 months ago
Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures
— Fault diagnosis has particular importance in the context of field programmable gate arrays (FPGAs) because faults can be avoided by reconfiguration at almost no real cost. Cl...
Ian G. Harris, Russell Tessier
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
13 years 9 months ago
Deterministic Test Pattern Generation Techniques for Sequential Circuits
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
Ilker Hamzaoglu, Janak H. Patel
ICCAD
2000
IEEE
78views Hardware» more  ICCAD 2000»
13 years 9 months ago
DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators
Kenneth Francken, Peter J. Vancorenland, Georges G...