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ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
13 years 9 months ago
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis
— Memory is one of the most important components to be optimized in the several phases of the synthesis process. ioral synthesis, a memory is viewed as an abstract construct whic...
Gernot Koch, Taewhan Kim, Reiner Genevriere
ICCAD
2000
IEEE
100views Hardware» more  ICCAD 2000»
13 years 9 months ago
Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering
For data dominated applications, the system level design trajectory should first focus on finding a good data transfer and storage solution. Since no realization details are avail...
Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. ...
ICCAD
2000
IEEE
169views Hardware» more  ICCAD 2000»
13 years 9 months ago
Transistor-Level Timing Analysis Using Embedded Simulation
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
Pawan Kulshreshtha, Robert Palermo, Mohammad Morta...
ICCAD
2000
IEEE
148views Hardware» more  ICCAD 2000»
13 years 9 months ago
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed t...
Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, ...
ICCAD
2000
IEEE
69views Hardware» more  ICCAD 2000»
13 years 9 months ago
Symbolic Debugging Scheme for Optimized Hardware and Software
Farinaz Koushanfar, Darko Kirovski, Miodrag Potkon...
ICCAD
2000
IEEE
65views Hardware» more  ICCAD 2000»
13 years 9 months ago
Predictable Routing
Predictable routing is the concept of using prespeci ed patterns to route a net. By doing this, we allow an more accurate prediction mechanism for metrics such as congestion and w...
Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzade...
ICCAD
2000
IEEE
148views Hardware» more  ICCAD 2000»
13 years 9 months ago
FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders
—As the complexity of digital filters is dominated by the number of multiplications, many works have focused on minimizing the complexity of multiplier blocks that compute the co...
Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park
ICCAD
2000
IEEE
99views Hardware» more  ICCAD 2000»
13 years 9 months ago
On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools
The incremental, “construct by correction” design methodology has become widespread in constraint-dominated DSM design. We study the problem of ECO for physical design domains...
Andrew B. Kahng, Stefanus Mantik
ICCAD
2000
IEEE
113views Hardware» more  ICCAD 2000»
13 years 9 months ago
Don't Cares and Multi-Valued Logic Network Minimization
We address optimizing multi-valued (MV) logic functions in a multi-level combinational logic network. Each node in the network, called an MV-node, has multi-valued inputs and sing...
Yunjian Jiang, Robert K. Brayton