ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that ...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper, we propose a novel fault-oriented test generation methodology for detection and isolation of faults in analog circuits. Given the description of the circuit-underte...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper, we present simulation techniques to estimate the worst-case voltage variation using a RC model for the power distribution network. Pattern independent maximum envel...