ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
This paper is concerned with finding timing-independent false paths that cannot be sensitized under any signal arrival time condition in integrated circuits. Existing techniques r...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
Trace buffer technology allows tracking the values of a few number of state elements inside a chip within a desired time window, which is used to analyze logic errors during post-s...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
3D stacked circuits reduce communication delay in multicore system-on-chips (SoCs) and enable heterogeneous integration of cores, memories, sensors, and RF devices. However, vertic...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
Abstract-- Many of us in the field of ultra-low-Vdd processors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper i...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
Abstract--More and more embedded systems provide a multitude of services, implemented by a large number of networked hardware components. In early design phases, dimensioning such ...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
State-based model checking methods comprise computing and storing reachable states, while stateless model checking methods directly reason about reachable paths using decision proc...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
Extreme technology scaling in silicon devices drastically affects reliability, particularly because of runtime failures induced by transistor wearout. Currently available online t...