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ISQED
2002
IEEE
72views Hardware» more  ISQED 2002»
11 years 6 months ago
Inductance Aware Interconnect Scaling
This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown...
Kaustav Banerjee, Amit Mehrotra
ISCAS
2005
IEEE
130views Hardware» more  ISCAS 2005»
11 years 7 months ago
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction
Inductance effects of on-chip interconnects have become more and more significant in today’s high-speed digital circuits, especially for global interconnects such as signal buse...
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
ISQED
2007
IEEE
160views Hardware» more  ISQED 2007»
11 years 8 months ago
On-Chip Inductance in X Architecture Enabled Design
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition tim...
Santosh Shah, Arani Sinha, Li Song, Narain D. Aror...
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