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DATE
2000
IEEE
71views Hardware» more  DATE 2000»
10 years 6 months ago
Clocktree RLC Extraction with Efficient Inductance Modeling
In this paper, we present an efficient yet accurate inductance extraction methodology and also apply it to clocktree RLC extraction. We first show that without loss of accuracy, t...
Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie...
IPPS
2002
IEEE
10 years 6 months ago
Fast Inductance Extraction of Large VLSI Circuits
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is do...
Hemant Mahawar, Vivek Sarin, Weiping Shi
HIPC
2004
Springer
10 years 7 months ago
Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction
Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
Hemant Mahawar, Vivek Sarin, Ananth Grama
ASPDAC
2006
ACM
106views Hardware» more  ASPDAC 2006»
10 years 7 months ago
Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method
— A complete multiple reciprocity method (CMRM), usually for the eigenvalue analysis of Helmholtz equation, is introduced to the BEM for frequency-dependent inductance extraction...
Changhao Yan, Wenjian Yu, Zeyi Wang
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