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ISCA
1999
IEEE
124views Hardware» more  ISCA 1999»
9 years 10 months ago
Speculation Techniques for Improving Load Related Instruction Scheduling
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for disp...
Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan...
ISCA
1999
IEEE
87views Hardware» more  ISCA 1999»
9 years 10 months ago
Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs
Several ILP limit studies indicate the presence of considerable ILP across dynamically far-apart instructions in program execution. This paper proposes a hardware mechanism, dynam...
Sriram Vajapeyam, P. J. Joseph, Tulika Mitra
ISCA
1999
IEEE
94views Hardware» more  ISCA 1999»
9 years 10 months ago
Storageless Value Prediction Using Prior Register Values
This paper presents a technique called register value prediction (RVP) which uses a type of locality called register-value reuse. By predicting that an instruction will produce th...
Dean M. Tullsen, John S. Seng
ISCA
1999
IEEE
90views Hardware» more  ISCA 1999»
9 years 10 months ago
Effective Jump-Pointer Prefetching for Linked Data Structures
Current techniques for prefetching linked data structures (LDS) exploit the work available in one loop iteration or recursive call to overlap pointer chasing latency. Jumppointers...
Amir Roth, Gurindar S. Sohi
ISCA
1999
IEEE
88views Hardware» more  ISCA 1999»
9 years 10 months ago
A Scalable Front-End Architecture for Fast Instruction Delivery
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
Glenn Reinman, Todd M. Austin, Brad Calder
ISCA
1999
IEEE
88views Hardware» more  ISCA 1999»
9 years 10 months ago
Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions
This paper aims to provide a quantitative understanding of the performance of image and video processing applications on general-purpose processors, without and with media ISA ext...
Parthasarathy Ranganathan, Sarita V. Adve, Norman ...
ISCA
1999
IEEE
95views Hardware» more  ISCA 1999»
9 years 10 months ago
Memory Sharing Predictor: The Key to a Speculative Coherent DSM
Recent research advocates using general message predictors to learn and predict the coherence activity in distributed shared memory (DSM). By accurately predicting a message and t...
An-Chow Lai, Babak Falsafi
ISCA
1999
IEEE
87views Hardware» more  ISCA 1999»
9 years 10 months ago
Memory Forwarding: Enabling Aggressive Layout Optimizations by Guaranteeing the Safety of Data Relocation
By optimizing data layout at run-time, we can potentially enhance the performance of caches by actively creating spatial locality, facilitating prefetching, and avoiding cache con...
Chi-Keung Luk, Todd C. Mowry
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
9 years 10 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
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