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ISCA
1999
IEEE

Speculation Techniques for Improving Load Related Instruction Scheduling

9 years 8 months ago
Speculation Techniques for Improving Load Related Instruction Scheduling
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for dispatching instructions to execution units based on dependencies, latencies, and resource availability. Most existing instruction schedulers are doing a less than optimal job of scheduling memory accesses and instructions dependent on them, for the following reasons:
Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where ISCA
Authors Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan Jourdan
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