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ISCA
2003
IEEE
123views Hardware» more  ISCA 2003»
10 years 5 months ago
Detecting Global Stride Locality in Value Streams
Value prediction exploits localities in value streams. Previous research focused on exploiting two types of value localities, computational and context-based, in the local value h...
Huiyang Zhou, Jill Flanagan, Thomas M. Conte
ISCA
2003
IEEE
124views Hardware» more  ISCA 2003»
10 years 5 months ago
A Highly-Configurable Cache Architecture for Embedded Systems
Chuanjun Zhang, Frank Vahid, Walid A. Najjar
ISCA
2003
IEEE
116views Hardware» more  ISCA 2003»
10 years 5 months ago
A "Flight Data Recorder" for Enabling Full-System Multiprocessor Deterministic Replay
Debuggers have been proven indispensable in improving software reliability. Unfortunately, on most real-life software, debuggers fail to deliver their most essential feature — a...
Min Xu, Rastislav Bodík, Mark D. Hill
ISCA
2003
IEEE
120views Hardware» more  ISCA 2003»
10 years 5 months ago
SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling
Roland E. Wunderlich, Thomas F. Wenisch, Babak Fal...
ISCA
2003
IEEE
110views Hardware» more  ISCA 2003»
10 years 5 months ago
Guided Region Prefetching: A Cooperative Hardware/Software Approach
Despite large caches, main-memory access latencies still cause significant performance losses in many applications. Numerous hardware and software prefetching schemes tolerate th...
Zhenlin Wang, Doug Burger, Steven K. Reinhardt, Ka...
ISCA
2003
IEEE
124views Hardware» more  ISCA 2003»
10 years 5 months ago
Banked Multiported Register Files for High-Frequency Superscalar Microprocessors
Multiported register files are a critical component of high-performance superscalar microprocessors. Conventional multiported structures can consume significant power and die ar...
Jessica H. Tseng, Krste Asanovic
ISCA
2003
IEEE
212views Hardware» more  ISCA 2003»
10 years 5 months ago
A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels
Trends in microprocessors of increasing die size and clock speed and decreasing feature sizes have fueled rapidly increasing performance. However, the limited improvements in DRAM...
Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi...
ISCA
2003
IEEE
108views Hardware» more  ISCA 2003»
10 years 5 months ago
Effective ahead Pipelining of Instruction Block Address Generation
On a N-way issue superscalar processor, the front end instruction fetch engine must deliver instructions to the execution core at a sustained rate higher than N instructions per c...
André Seznec, Antony Fraboulet
ISCA
2003
IEEE
168views Hardware» more  ISCA 2003»
10 years 5 months ago
Temperature-Aware Microarchitecture
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processo...
Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakuma...
ISCA
2003
IEEE
130views Hardware» more  ISCA 2003»
10 years 5 months ago
GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks
We introduce a load-balanced adaptive routing algorithm for torus networks, GOAL - Globally Oblivious Adaptive Locally - that provides high throughput on adversarial traffic patt...
Arjun Singh, William J. Dally, Amit K. Gupta, Bria...
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