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ISCA
2003
IEEE
107views Hardware» more  ISCA 2003»
13 years 10 months ago
Positional Adaptation of Processors: Application to Energy Reduction
Although adaptive processors can exploit application variability to improve performance or save energy, effectively managing their adaptivity is challenging. To address this probl...
Michael C. Huang, Jose Renau, Josep Torrellas
ISCA
2003
IEEE
83views Hardware» more  ISCA 2003»
13 years 10 months ago
Efficient Use of Memory Bandwidth to Improve Network Processor Throughput
Jahangir Hasan, Satish Chandra, T. N. Vijaykumar
ISCA
2003
IEEE
136views Hardware» more  ISCA 2003»
13 years 10 months ago
Transient-Fault Recovery for Chip Multiprocessors
To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR...
Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz,...
ISCA
2003
IEEE
150views Hardware» more  ISCA 2003»
13 years 10 months ago
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
Dan Ernst, Andrew Hamel, Todd M. Austin
ISCA
2003
IEEE
183views Hardware» more  ISCA 2003»
13 years 10 months ago
The Jrpm System for Dynamically Parallelizing Java Programs
We describe the Java runtime parallelizing machine (Jrpm), a complete system for parallelizing sequential programs automatically. Jrpm is based on a chip multiprocessor (CMP) with...
Michael K. Chen, Kunle Olukotun
ISCA
2003
IEEE
99views Hardware» more  ISCA 2003»
13 years 10 months ago
DISE: A Programmable Macro Engine for Customizing Applications
Marc L. Corliss, E. Christopher Lewis, Amir Roth
ISCA
2003
IEEE
89views Hardware» more  ISCA 2003»
13 years 10 months ago
MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences
A majority of the papers published in leading computer architecture conferences use SPEC CPU2000, or its predecessor SPEC CPU95, which has become the de facto standard for measuri...
Daniel Citron
ISCA
2003
IEEE
93views Hardware» more  ISCA 2003»
13 years 10 months ago
Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors
This work examines dynamic cluster assignment for a clustered trace cache processor (CTCP). Previously proposed cluster assignment techniques run into unique problems as issue wid...
Ravi Bhargava, Lizy Kurian John
ISCA
2003
IEEE
169views Hardware» more  ISCA 2003»
13 years 10 months ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, ...
ISCA
2003
IEEE
88views Hardware» more  ISCA 2003»
13 years 10 months ago
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors
Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-d...
Rajeev Balasubramonian, Sandhya Dwarkadas, David H...