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ISCA
2005
IEEE
135views Hardware» more  ISCA 2005»
13 years 10 months ago
Deconstructing Commodity Storage Clusters
The traditional approach for characterizing complex systems is to run standard workloads and measure the resulting performance as seen by the end user. However, unique opportuniti...
Haryadi S. Gunawi, Nitin Agrawal, Andrea C. Arpaci...
ISCA
2005
IEEE
104views Hardware» more  ISCA 2005»
13 years 10 months ago
Opportunistic Transient-Fault Detection
CMOS scaling increases susceptibility of microprocessors to transient faults. Most current proposals for transient-fault detection use full redundancy to achieve perfect coverage ...
Mohamed A. Gomaa, T. N. Vijaykumar
ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
13 years 10 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
ISCA
2005
IEEE
99views Hardware» more  ISCA 2005»
13 years 10 months ago
Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking
To maintain coherence in conventional shared-memory multiprocessor systems, processors first check other processors’ caches before obtaining data from memory. This coherence che...
Jason F. Cantin, Mikko H. Lipasti, James E. Smith
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
13 years 10 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
ISCA
2005
IEEE
90views Hardware» more  ISCA 2005»
13 years 10 months ago
Optimizing Replication, Communication, and Capacity Allocation in CMPs
Chip multiprocessors (CMPs) substantially increase capacity pressure on the on-chip memory hierarchy while requiring fast access. Neither private nor shared caches can provide bot...
Zeshan Chishti, Michael D. Powell, T. N. Vijaykuma...
ISCA
2005
IEEE
162views Hardware» more  ISCA 2005»
13 years 10 months ago
Mitigating Amdahl's Law through EPI Throttling
Murali Annavaram, Ed Grochowski, John Paul Shen
ISCA
2005
IEEE
128views Hardware» more  ISCA 2005»
13 years 10 months ago
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures
: The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical...
Steven Balensiefer, Lucas Kreger-Stickles, Mark Os...
ISCA
2005
IEEE
81views Hardware» more  ISCA 2005»
13 years 10 months ago
The Impact of Performance Asymmetry in Emerging Multicore Architectures
Performance asymmetry in multicore architectures arises when individual cores have different performance. Building such multicore processors is desirable because many simple cores...
Saisanthosh Balakrishnan, Ravi Rajwar, Michael Upt...
ISCA
2005
IEEE
126views Hardware» more  ISCA 2005»
13 years 10 months ago
A Tree Based Router Search Engine Architecture with Single Port Memories
Pipelined forwarding engines are used in core routers to meet speed demands. Tree-based searches are pipelined across a number of stages to achieve high throughput, but this resul...
Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Su...