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ISCA
2005
IEEE
154views Hardware» more  ISCA 2005»
9 years 1 months ago
Temporal Streaming of Shared Memory
Coherent read misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. We propose Tempor...
Thomas F. Wenisch, Stephen Somogyi, Nikolaos Harda...
ISCA
2005
IEEE
99views Hardware» more  ISCA 2005»
9 years 1 months ago
Store Buffer Design in First-Level Multibanked Data Caches
Enrique F. Torres, Pablo Ibáñez, V&i...
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
9 years 1 months ago
A High Throughput String Matching Architecture for Intrusion Detection and Prevention
Network Intrusion Detection and Prevention Systems have emerged as one of the most effective ways of providing security to those connected to the network, and at the heart of alm...
Lin Tan, Timothy Sherwood
ISCA
2005
IEEE
166views Hardware» more  ISCA 2005»
9 years 1 months ago
Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
Emil Talpes, Diana Marculescu
ISCA
2005
IEEE
105views Hardware» more  ISCA 2005»
9 years 1 months ago
Exploiting Structural Duplication for Lifetime Reliability Enhancement
Increased power densities (and resultant temperatures) and other effects of device scaling are predicted to cause significant lifetime reliability problems in the near future. In...
Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, J...
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
9 years 1 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
ISCA
2005
IEEE
101views Hardware» more  ISCA 2005»
9 years 1 months ago
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
Minimizing latency and maximizing throughput are important goals in the design of routing algorithms for interconnection networks. Ideally, we would like a routing algorithm to (a...
Daeho Seo, Akif Ali, Won-Taek Lim, Nauman Rafique,...
ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
9 years 1 months ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar
ISCA
2005
IEEE
91views Hardware» more  ISCA 2005»
9 years 1 months ago
High Efficiency Counter Mode Security Architecture via Prediction and Precomputation
Weidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, Che...
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