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ISQED
2002
IEEE
83views Hardware» more  ISQED 2002»
13 years 9 months ago
A Hybrid BIST Architecture and Its Optimization for SoC Testing
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
ISQED
2002
IEEE
123views Hardware» more  ISQED 2002»
13 years 9 months ago
Reliable Laser Programmable Gate Array Technology
Field-Programmable Gate Arrays have become popular
Zhuo Gao, Ji Luo, Hu Huang, Wei Zhang, Joseph B. B...
ISQED
2002
IEEE
72views Hardware» more  ISQED 2002»
13 years 9 months ago
Inductance Aware Interconnect Scaling
This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown...
Kaustav Banerjee, Amit Mehrotra
ISQED
2002
IEEE
126views Hardware» more  ISQED 2002»
13 years 9 months ago
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-...
ISQED
2002
IEEE
137views Hardware» more  ISQED 2002»
13 years 9 months ago
A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits
In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit ar...
Syed M. Alam, Donald E. Troxel, Carl V. Thompson
ISQED
2002
IEEE
103views Hardware» more  ISQED 2002»
13 years 9 months ago
Synthesis of Selectively Clocked Skewed Logic Circuits
Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaush...
ISQED
2002
IEEE
168views Hardware» more  ISQED 2002»
13 years 9 months ago
ALBORZ: Address Level Bus Power Optimization
In this paper we introduce a new low power address bus encoding technique, and the resulting code, named ALBORZ. The ALBORZ code is constructed based on transition signaling the l...
Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram
ISQED
2002
IEEE
74views Hardware» more  ISQED 2002»
13 years 9 months ago
Wireless Systems-on-a-Chip Design
B. Brodersen
ISQED
2002
IEEE
203views Hardware» more  ISQED 2002»
13 years 9 months ago
Automatic Test Program Generation from RT-Level Microprocessor Descriptions
The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach based on the generation of a test program. The proposed method relies on two p...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...