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ISVLSI
2006
IEEE
112views VLSI» more  ISVLSI 2006»
12 years 3 months ago
Multiprocessor Systems-on-Chips
Wayne Wolf
ISVLSI
2006
IEEE
129views VLSI» more  ISVLSI 2006»
12 years 3 months ago
Connection-oriented Multicasting in Wormhole-switched Networks on Chip
Network-on-Chip (NoC) proposes networks to replace buses as a scalable global communication interconnect for future SoC designs. However, a bus is very efficient in broadcasting....
Zhonghai Lu, Bei Yin, Axel Jantsch
ISVLSI
2006
IEEE
137views VLSI» more  ISVLSI 2006»
12 years 3 months ago
Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems
This paper presents the low power implementation of a Maximum Likelihood (ML) based detector used in the receiver part of a Multiple Input and Multiple Output (MIMO) systems. Low ...
T. Takahashi, Ahmet T. Erdogan, Tughrul Arslan, J....
ISVLSI
2006
IEEE
115views VLSI» more  ISVLSI 2006»
12 years 3 months ago
The Design of Analog Front-End Circuitry for 1X HD-DVD PRML Read Channel
In this paper, the design techniques and considerations for each building block required for analog signal processing in HD-DVD PRML read channel are presented and the procedures ...
Sheng-Jang Lin, I-Shun Chen, Bo-Wei Chen, Feng-Hsi...
ISVLSI
2006
IEEE
104views VLSI» more  ISVLSI 2006»
12 years 3 months ago
Adaptive Signal Processing in Mixed-Signal VLSI with Anti-Hebbian Learning
We describe analog and mixed-signal primitives for implementing adaptive signal-processing algorithms in VLSI based on anti-Hebbian learning. Both on-chip calibration techniques a...
Miguel Figueroa, Esteban Matamala, Gonzalo Carvaja...
ISVLSI
2006
IEEE
105views VLSI» more  ISVLSI 2006»
12 years 3 months ago
Floorplanning Based on Particle Swarm Optimization
Tsung-Ying Sun, Sheng-Ta Hsieh, Hsiang-Min Wang, C...
ISVLSI
2006
IEEE
150views VLSI» more  ISVLSI 2006»
12 years 3 months ago
Design and Analysis of a Low Power VLIW DSP Core
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
Chan-Hao Chang, Diana Marculescu
ISVLSI
2006
IEEE
149views VLSI» more  ISVLSI 2006»
12 years 3 months ago
Defect-Aware Design Paradigm for Reconfigurable Architectures
With advances in process technology, the feature sizes are decreasing, which leads to higher defect densities. More sophisticated techniques, at increased costs are required to av...
Rahul Jain, Anindita Mukherjee, Kolin Paul
ISVLSI
2006
IEEE
88views VLSI» more  ISVLSI 2006»
12 years 3 months ago
Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks
— The effects of parameter variations and crosstalk noise on the clock signal propagating along an H-tree clock distribution network are investigated in this paper. In particular...
Itisha Chanodia, Dimitrios Velenis
ISVLSI
2006
IEEE
106views VLSI» more  ISVLSI 2006»
12 years 3 months ago
Self-Timed Thermally-Aware Circuits
Thermal management is becoming increasingly important in circuit designs with high power density. Circuits that overheat beyond specified operating conditions may suffer timing f...
David Fang, Filipp Akopyan, Rajit Manohar
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