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ISVLSI
2006
IEEE
126views VLSI» more  ISVLSI 2006»
13 years 11 months ago
QUKU: A Two-Level Reconfigurable Architecture
FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfig...
Sunil Shukla, Neil W. Bergmann, Jürgen Becker
ISVLSI
2006
IEEE
82views VLSI» more  ISVLSI 2006»
13 years 11 months ago
Reliability-Aware SOC Voltage Islands Partition and Floorplan
— Based on the proposed reliability characterization model, reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip d...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
ISVLSI
2006
IEEE
115views VLSI» more  ISVLSI 2006»
13 years 11 months ago
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems
This paper investigates the performance and power dissipation of Globally Asynchronous Locally Synchronous (GALS) multi-processor systems. We show that communication loops are a s...
Zhiyi Yu, Bevan M. Baas