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ITC
1997
IEEE
80views Hardware» more  ITC 1997»
13 years 9 months ago
Scan Synthesis for One-Hot Signals
Tri-state buses and pass transistor logic are used in many complex applications to achieve high performance and small area. Such circuits often contain logic requiring one-hot sig...
Subhasish Mitra, LaNae J. Avra, Edward J. McCluske...
ITC
1997
IEEE
107views Hardware» more  ITC 1997»
13 years 9 months ago
Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique
The detection of cell stability and data retention faults in SRAMs has been a time consuming process. In this paper we discuss a new design for test technique called Weak Write Tes...
Anne Meixner, Jash Banik
ITC
1997
IEEE
90views Hardware» more  ITC 1997»
13 years 9 months ago
Bridging Fault Diagnosis in the Absence of Physical Information
David B. Lavo, Tracy Larrabee, F. Joel Ferguson, B...
ITC
1997
IEEE
60views Hardware» more  ITC 1997»
13 years 9 months ago
Using BIST Control for Pattern Generation
A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It take...
Gundolf Kiefer, Hans-Joachim Wunderlich
ITC
1997
IEEE
73views Hardware» more  ITC 1997»
13 years 9 months ago
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
ITC
1997
IEEE
60views Hardware» more  ITC 1997»
13 years 9 months ago
Current Signatures: Application
Analysis of IC technology trends indicates that Iddq testing may be approaching its limits of applicability. The new concept of the current signature may expand this limit under t...
Anne E. Gattiker, Wojciech Maly
ITC
1997
IEEE
129views Hardware» more  ITC 1997»
13 years 9 months ago
On Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...
ITC
1997
IEEE
100views Hardware» more  ITC 1997»
13 years 9 months ago
Signal Generation Using Periodic Single-and Multi-Bit Sigma-Delta Modulated Streams
Abstract- This paper describes a new method to generate analog signals with high precision at very low hardware complexity. This method consists in reproducing periodically a recor...
Benoit Dufort, Gordon W. Roberts