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PATMOS
2005
Springer
12 years 2 days ago
A Power-Efficient and Scalable Load-Store Queue Design
Abstract. The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed a...
Fernando Castro, Daniel Chaver, Luis Piñuel...
HPCA
2006
IEEE
12 years 7 months ago
Software-hardware cooperative memory disambiguation
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
Ruke Huang, Alok Garg, Michael C. Huang
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