Sciweavers

Share
warning: Creating default object from empty value in /var/www/modules/taxonomy/taxonomy.module on line 1416.
CSREAESA
2006
11 years 6 months ago
Delay-Reduced Combinational Logic Synthesis using Multiplexers
- This paper presents an approach to obtain reduced hardware and/or delay for synthesizing logic functions using multiplexers. Replication of single control line multiplexer is use...
Rekha K. James, T. K. Shahana, K. Poulose Jacob, S...
EUROGP
2000
Springer
116views Optimization» more  EUROGP 2000»
11 years 8 months ago
An Extrinsic Function-Level Evolvable Hardware Approach
1 The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in rst time. The new representation of logic...
Tatiana Kalganova
FPL
2005
Springer
96views Hardware» more  FPL 2005»
11 years 10 months ago
FPGA PLB Evaluation using Quantified Boolean Satisfiability
This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...
books