Sciweavers

ADC
2000
Springer
326views Database» more  ADC 2000»
13 years 9 months ago
T-Tree or B-Tree: Main Memory Database Index Structure Revisited
While the B-tree (or the B+ -tree) is the most popular index structure in disk-based relational database systems, the Ttree has been widely accepted as a promising index structure...
Hongjun Lu, Yuet Yeung Ng, Zengping Tian
SSDBM
2000
IEEE
86views Database» more  SSDBM 2000»
13 years 9 months ago
Serving Datacube Tuples from Main Memory
Existing datacube precompuatation schemes materialize selected datacube tuples on disk, choosing the most beneficial cuboids (i.e., combinations of dimensions) to materialize giv...
Kenneth A. Ross, Kazi A. Zaman
GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
13 years 9 months ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
13 years 9 months ago
Using a User-Level Memory Thread for Correlation Prefetching
This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main ...
Yan Solihin, Josep Torrellas, Jaejin Lee
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
13 years 9 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ICCS
2003
Springer
13 years 9 months ago
A Compress-Based Association Mining Algorithm for Large Dataset
The association mining is one of the primary sub-areas in the field of data mining. This technique had been used in numerous practical applications, including consumer market baske...
Mafruz Zaman Ashrafi, David Taniar, Kate A. Smith
PPOPP
2003
ACM
13 years 9 months ago
Programming the FlexRAM parallel intelligent memory system
In an intelligent memory architecture, the main memory of a computer is enhanced with many simple processors. The result is a highly-parallel, heterogeneous machine that is able t...
Basilio B. Fraguela, Jose Renau, Paul Feautrier, D...
RTSS
2003
IEEE
13 years 9 months ago
Impact of PCI-Bus Load on Applications in a PC Architecture
Any data exchanged between the processor and main memory uses the memory bus, sharing it with data exchanged between I/O devices and main memory. If the processor and a device try...
Sebastian Schönberg
ITCC
2003
IEEE
13 years 9 months ago
Fast Prefix Code Processing
As large main memory becomes more and more available at reasonable prices, processing speed of large data sets becomes more important than reducing main memory usage of internal d...
Renato Pajarola
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
13 years 9 months ago
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors
This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the domi...
Alberto Macii, Enrico Macii, Fabrizio Crudo, Rober...