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GLVLSI
2007
IEEE
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14 years 1 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
WAIM
2007
Springer
14 years 3 months ago
Building Data Synopses Within a Known Maximum Error Bound
The constructions of Haar wavelet synopses for large data sets have proven to be useful tools for data approximation. Recently, research on constructing wavelet synopses with a gua...
Chaoyi Pang, Qing Zhang, David P. Hansen, Anthony ...
MICCAI
2003
Springer
14 years 10 months ago
A Spatial-Stiffness Analysis of Fiducial Registration Accuracy
Abstract. We describe a new approach to predicting the maximum target registration error for fiducial registration. The approach is based on the analysis of a spatial stiffness mod...
Burton Ma, Randy E. Ellis