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MICRO
1995
IEEE
125views Hardware» more  MICRO 1995»
9 years 3 months ago
Disjoint eager execution: an optimal form of speculative execution
Instruction Level Parallelism (ILP) speedups of an order-of-magnitude or greater may be possible using the techniques described herein. Traditional speculative code execution is t...
Augustus K. Uht, Vijay Sindagi, Kelley Hall
MICRO
1995
IEEE
97views Hardware» more  MICRO 1995»
9 years 3 months ago
Improving CISC instruction decoding performance using a fill unit
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
Mark Smotherman, Manoj Franklin
MICRO
1995
IEEE
72views Hardware» more  MICRO 1995»
9 years 3 months ago
Critical path reduction for scalar programs
Michael S. Schlansker, Vinod Kathail
MICRO
1995
IEEE
108views Hardware» more  MICRO 1995»
9 years 3 months ago
SPAID: software prefetching in pointer- and call-intensive environments
Software prefetching, typically in the context of numericor loop-intensive benchmarks, has been proposed as one remedy for the performance bottleneck imposed on computer systems b...
Mikko H. Lipasti, William J. Schmidt, Steven R. Ku...
MICRO
1995
IEEE
93views Hardware» more  MICRO 1995»
9 years 3 months ago
Unrolling-based optimizations for modulo scheduling
Daniel M. Lavery, Wen-mei W. Hwu
MICRO
1995
IEEE
94views Hardware» more  MICRO 1995»
9 years 3 months ago
Region-based compilation: an introduction and motivation
Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Ra...
MICRO
1995
IEEE
81views Hardware» more  MICRO 1995»
9 years 3 months ago
The M-Machine multicomputer
Marco Fillo, Stephen W. Keckler, William J. Dally,...
MICRO
1995
IEEE
217views Hardware» more  MICRO 1995»
9 years 3 months ago
Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
Jack W. Davidson, Sanjay Jinturkar
MICRO
1995
IEEE
102views Hardware» more  MICRO 1995»
9 years 3 months ago
Zero-cycle loads: microarchitecture support for reducing load latency
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
Todd M. Austin, Gurindar S. Sohi
MICRO
1995
IEEE
85views Hardware» more  MICRO 1995»
9 years 3 months ago
The predictability of branches in libraries
Brad Calder, Dirk Grunwald, Amitabh Srivastava
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