MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
Instruction Level Parallelism (ILP) speedups of an order-of-magnitude or greater may be possible using the techniques described herein. Traditional speculative code execution is t...
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
Software prefetching, typically in the context of numericor loop-intensive benchmarks, has been proposed as one remedy for the performance bottleneck imposed on computer systems b...
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE