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    FPL
    2004
    Springer
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    Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis
    13 years 9 months ago
    Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis
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    Abstract. Layout tools for FPGAs can typically be run in two different modes: non-timing-driven and timing-driven. Non-timing-driven mode produces a solution quickly, without consi...
    Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, ...
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