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FPGA
2000
ACM
145views FPGA» more  FPGA 2000»
12 years 3 months ago
A C compiler for a processor with a reconfigurable functional unit
This paper describes a C compiler for a mixed Processor/FPGA architecture where the FPGA is a Reconfigurable Functional Unit (RFU). It presents three compilation techniques that c...
Zhi Alex Ye, U. Nagaraj Shenoy, Prithviraj Banerje...
FPL
2006
Springer
95views Hardware» more  FPL 2006»
12 years 3 months ago
A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor
This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target application...
Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, K...
RSP
1999
IEEE
128views Control Systems» more  RSP 1999»
12 years 3 months ago
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems
The advances in the programmable hardware has lead to new architectures where the hardware can be dynamically adapted to the application to gain better performance. There are stil...
Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
DATE
2002
IEEE
114views Hardware» more  DATE 2002»
12 years 4 months ago
A Video Compression Case Study on a Reconfigurable VLIW Architecture
In this paper, we investigate the benefits of a flexible, application-specific instruction set by adding a run-time Reconfigurable Functional Unit (RFU) to a VLIW processor. Preli...
Davide Rizzo, Osvaldo Colavin
VLSI
2007
Springer
12 years 5 months ago
An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor
Replacing functional units of an extensible processor with reconfigurable functional units enhances performance and flexibility of processors to execute custom instructions. That ...
Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Za...
VLSID
2002
IEEE
125views VLSI» more  VLSID 2002»
12 years 12 months ago
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
Francisco Barat, Murali Jayapala, Pieter Op de Bee...
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