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NOCS
2010
IEEE
11 years 11 months ago
Design of a High-Throughput Distributed Shared-Buffer NoC Router
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...
Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin,...
ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
11 years 12 months ago
Improved on-chip router analytical power and area modeling
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence o...
Andrew B. Kahng, Bill Lin, Kambiz Samadi
JCM
2010
119views more  JCM 2010»
12 years 10 days ago
Evaluation of Router Implementations for Explicit Congestion Control Schemes
— Explicit congestion control schemes use router feedback to overcome limitations of the standard mechanisms of the Transmission Control Protocol (TCP). These approaches require ...
Simon Hauger, Michael Scharf, Jochen Kögel, C...
INFOCOM
2010
IEEE
12 years 10 days ago
Non-Preemptive Buffer Management for Latency Sensitive Packets
—The delivery of latency sensitive packets is a crucial issue in real time applications of communication networks. Such packets often have a firm deadline and a packet becomes u...
Moran Feldman, Joseph Naor
NETWORKS
2007
12 years 1 months ago
Survivable IP network design with OSPF routing
Internet protocol (IP) traffic follows rules established by routing protocols. Shortest path based protocols, such as Open Shortest Path First (OSPF), direct traffic based on arc w...
Luciana S. Buriol, Mauricio G. C. Resende, Mikkel ...
TPDS
2002
142views more  TPDS 2002»
12 years 1 months ago
MediaWorm: A QoS Capable Router Architecture for Clusters
With the increasing use of clusters in real-time applications, it has become essential to design high performance networks with Quality-of-ServiceQoS guarantees. In this paper, we...
Ki Hwan Yum, Eun Jung Kim, Chita R. Das, Aniruddha...
TPDS
2002
105views more  TPDS 2002»
12 years 1 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
TON
1998
142views more  TON 1998»
12 years 1 months ago
A 50-Gb/s IP router
—Aggressive research on gigabit-per-second networks has led to dramatic improvements in network transmission speeds. One result of these improvements has been to put pressure on ...
Craig Partridge, Philip P. Carvey, Ed Burgess, Isi...
CN
1998
66views more  CN 1998»
12 years 1 months ago
Route Servers for Inter-Domain Routing
Internet transmission and switching facilities are partitioned into different administrative domains. To effect routing between domains, domain border routers establish pairwise p...
Ramesh Govindan, Cengiz Alaettinoglu, Kannan Varad...
CN
2002
91views more  CN 2002»
12 years 1 months ago
VERA: an extensible router architecture
We recognize two trends in router design: increasing pressure to extend the set of services provided by the router and increasing diversity in the hardware components used to cons...
Scott Karlin, Larry L. Peterson
books