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SASP
2009
IEEE
291views Hardware» more  SASP 2009»
13 years 11 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...
SASP
2009
IEEE
238views Hardware» more  SASP 2009»
13 years 11 months ago
Hardware acceleration of multi-view face detection
—This paper presents a parallelized architecture for hardware acceleration of multi-view face detection. In our architecture, the multi-view face detection system generates rotat...
Junguk Cho, Bridget Benson, Ryan Kastner
SASP
2009
IEEE
222views Hardware» more  SASP 2009»
13 years 11 months ago
A memory optimization technique for software-managed scratchpad memory in GPUs
—With the appearance of massively parallel and inexpensive platforms such as the G80 generation of NVIDIA GPUs, more real-life applications will be designed or ported to these pl...
Maryam Moazeni, Alex A. T. Bui, Majid Sarrafzadeh
SASP
2009
IEEE
170views Hardware» more  SASP 2009»
13 years 11 months ago
Parade: A versatile parallel architecture for accelerating pulse train clustering
— In this paper, we present Parade, a novel and flexible parallel architecture for the deinterleaving of combined pulsetrains. This is a commonly performed task in various areas ...
Amin Ansari, Dan Zhang, Scott A. Mahlke
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
13 years 11 months ago
A parameterisable and scalable Smith-Waterman algorithm implementation on CUDA-compatible GPUs
—This paper describes a multi-threaded parallel design and implementation of the Smith-Waterman (SM) algorithm on compute unified device architecture (CUDA)-compatible graphic pr...
Cheng Ling, Khaled Benkrid, Tsuyoshi Hamada
SASP
2009
IEEE
222views Hardware» more  SASP 2009»
13 years 11 months ago
Arithmetic optimization for custom instruction set synthesis
Abstract—One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arit...
Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne
SASP
2009
IEEE
156views Hardware» more  SASP 2009»
13 years 11 months ago
Introducing control-flow inclusion to support pipelining in custom instruction set extensions
—Multi-cycle Instruction set extensions (ISE) can be pipelined in order to increase their throughput; however, typical program traces seldom contain consecutive calls to the same...
Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel ...