SLIP
2009
ACM
13 years 12 months ago
2009
ACM
SLIP
2009
ACM
13 years 12 months ago
2009
ACM
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
SLIP
2009
ACM
13 years 12 months ago
2009
ACM
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...