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2009
ACM

Predicting the worst-case voltage violation in a 3D power network

9 years 8 months ago
Predicting the worst-case voltage violation in a 3D power network
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering leakage current. We first describe the 3D Power Distribution Network (PDN) structure which includes on-chip inductance and through-silicon-vias (TSV). The analysis flow using a superposition technique will be introduced later on. Then, we propose a general model to identify the worst-case gating pattern and the maximum variation area with arbitrary leakage current. For low power wireless chips, we introduce another simplified model, which treats the leakage to be a DC current. We formulate these two models with integer linear programming (ILP). The ILP based method is significantly faster than a conventional method based on enumeration. The experimental results also show that the noise contributed by leakage current is not negligible. Categories and Subject Descriptors J.6 [COMPUTER-AIDED ENGINEERING]: Compute...
Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shaya
Added 28 May 2010
Updated 28 May 2010
Type Conference
Year 2009
Where SLIP
Authors Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng
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