Sciweavers

    SIPS
    2007
    IEEE
    148views Signal Processing» more  SIPS 2007»
    An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding
    13 years 11 months ago
    An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding
    Download  www.iml.ece.mcgill.ca
    Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
    Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.