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COMCOM
1999
78views more  COMCOM 1999»
9 years 5 months ago
A complete test sequence using cyclic sequence for conformance testing
We present a problem of commonly used characterization sequences (CS) for the protocol conformance testing and propose a new test sequence to resolve the problem. The proposed tes...
DaeHun Nyang, S. Y. Lim, JooSeok Song
CN
1999
100views more  CN 1999»
9 years 5 months ago
Testing protocols modeled as FSMs with timing parameters
An optimization method is introduced for generating minimum-length test sequences taking into account timing constraints for FSM models of communication protocols. Due to active t...
M. Ümit Uyar, Mariusz A. Fecko, Adarshpal S. ...
JCP
2008
114views more  JCP 2008»
9 years 5 months ago
IntelligenTester - Test Sequence Optimization Framework using Multi-Agents
- Our paper focuses on the generation of optimal test sequences and test cases using Intelligent Agents for highly reliable systems. Test sequences support test case generation for...
D. Jeya Mala, V. Mohan
ASE
2006
123views more  ASE 2006»
9 years 5 months ago
Separating sequence overlap for automated test sequence generation
Finite state machines have been used to model a number of classes of system and there has thus been much interest in the automatic generation of test sequences from finite state m...
Robert M. Hierons
FORTE
2003
9 years 7 months ago
QoS Functional Testing for Multi-media Systems
Abstract. In this paper, we propose a testing method for QoS functions in distributed multi-media systems, where we test whether playback of media objects is correctly implemented ...
Tao Sun, Keiichi Yasumoto, Masaaki Mori, Teruo Hig...
ITC
1997
IEEE
129views Hardware» more  ITC 1997»
9 years 10 months ago
On Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...
DATE
1997
IEEE
100views Hardware» more  DATE 1997»
9 years 10 months ago
On the generation of pseudo-deterministic two-patterns test sequence with LFSRs
Many Built-In Self Test pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs o...
Christian Dufaza, Yervant Zorian
EVOW
1999
Springer
9 years 10 months ago
Test Pattern Generation Under Low Power Constraints
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...
ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
9 years 10 months ago
An approach for improving the levels of compaction achieved by vector omission
We describe a method referred to as sequence counting to improve on the levels of compaction achievable by vector omission based static compaction procedures. Such procedures are ...
Irith Pomeranz, Sudhakar M. Reddy
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
9 years 11 months ago
Test compaction for transition faults under transparent-scan
Transparent-scan was proposed as an approach to test generation and test compaction for scan circuits. Its effectiveness was demonstrated earlier in reducing the test application ...
Irith Pomeranz, Sudhakar M. Reddy
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