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JCP
2008
174views more  JCP 2008»
9 years 11 months ago
Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs
Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding ...
Kaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan
ISLPED
1995
ACM
114views Hardware» more  ISLPED 1995»
10 years 3 months ago
Power and area optimization by reorganizing CMOS complex gate circuits
Thispaper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor lay...
M. Tachibana, S. Kurosawa, R. Nojima, Norman Kojim...
ISLPED
1995
ACM
193views Hardware» more  ISLPED 1995»
10 years 3 months ago
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
Manjit Borah, Robert Michael Owens, Mary Jane Irwi...
ASPDAC
1999
ACM
143views Hardware» more  ASPDAC 1999»
10 years 4 months ago
Crosstalk Reduction by Transistor Sizing
In this paper we consider transistor sizing to reduce crosstalk. First, crosstalk noise dependency on wire width, wire spacing, driver and receiver sizes are discussed, and valida...
Tong Xiao, Malgorzata Marek-Sadowska
DATE
2002
IEEE
95views Hardware» more  DATE 2002»
10 years 4 months ago
Optimal Transistor Tapering for High-Speed CMOS Circuits
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
Li Ding 0002, Pinaki Mazumder
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