Sciweavers

TVLSI
2008
116views more  TVLSI 2008»
13 years 4 months ago
Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs
Abstract--In this paper, we introduce a novel substrate noise estimation technique during early floorplanning for mixed signal system-on-chip (SOC), based on block preference direc...
Minsik Cho, David Z. Pan
TVLSI
2008
140views more  TVLSI 2008»
13 years 4 months ago
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
Jorge Campos, Hussain Al-Asaad
TVLSI
2008
123views more  TVLSI 2008»
13 years 4 months ago
Cost-Efficient SHA Hardware Accelerators
Abstract--This paper presents a new set of techniques for hardware implementations of Secure Hash Algorithm (SHA) hash functions. These techniques consist mostly in operation resch...
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Sta...
TVLSI
2008
107views more  TVLSI 2008»
13 years 4 months ago
Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs
Thermal hot spots and high temperature gradients degrade reliability and performance, and increase cooling costs and leakage power. In this paper, we explore the benefits of temper...
Ayse Kivilcim Coskun, T. T. Rosing, Keith Whisnant...
TVLSI
2008
112views more  TVLSI 2008»
13 years 4 months ago
System Architecture and Implementation of MIMO Sphere Decoders on FPGA
Multiple-input
Xin-Ming Huang, Cao Liang, Jing Ma
TVLSI
2008
89views more  TVLSI 2008»
13 years 4 months ago
Scalable Multigigabit Pattern Matching for Packet Inspection
Ioannis Sourdis, Dionisios N. Pnevmatikatos, Stama...
TVLSI
2008
149views more  TVLSI 2008»
13 years 4 months ago
Architectural Modifications to Enhance the Floating-Point Performance of FPGAs
With the density of FPGAs steadily increasing, FPGAs have reached the point where they are capable of implementing complex floating-point applications. However, their general-purpo...
Michael J. Beauchamp, Scott Hauck, Keith D. Underw...
TVLSI
2008
121views more  TVLSI 2008»
13 years 4 months ago
Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores
Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-p...
Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna
TVLSI
2008
133views more  TVLSI 2008»
13 years 4 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias
TVLSI
2008
132views more  TVLSI 2008»
13 years 4 months ago
Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware
Mobile wireless terminals tend to become multimode wireless communication devices. Furthermore, these devices become adaptive. Heterogeneous reconfigurable hardware provides the fl...
Gerard K. Rauwerda, Paul M. Heysters, Gerard J. M....