Sciweavers

Share
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
9 years 2 months ago
Quality considerations in delay fault testing
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
Alicja Pierzynska, Slawomir Pilarski
books