VLSID
1996
IEEE
13 years 9 months ago
1996
IEEE
VLSID
1996
IEEE
13 years 9 months ago
1996
IEEE
VLSID
1996
IEEE
13 years 9 months ago
1996
IEEE
VLSID
1996
IEEE
13 years 9 months ago
1996
IEEE
This paper presents VLSI/WSI designs for a recently introduced parallel architecture known as the folded cube-connected cycles (FCCC). We first discuss two layouts for the FCCC, i...
VLSID
1996
IEEE
13 years 9 months ago
1996
IEEE
Existing systolic architectures for the LMS algorithm with delayed coeficient adaptation have large adaptation delay and hence degraded convergence behaviour. This paper presents ...
VLSID
1996
IEEE
13 years 9 months ago
1996
IEEE
Reduced Ordered Binary Decision Diagrams ROBDDs have traditionally been built in a bottom-up fashion. In this scheme, the intermediate peak memory utilization is often larger than...
VLSID
1996
IEEE
13 years 9 months ago
1996
IEEE
The technique of mirror biasing is introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize its output voltage to bias variations. Various...
VLSID
1996
IEEE
13 years 9 months ago
1996
IEEE
A technique for allocatzon and binding for data path synthesis (DPS) using a Genetic Algorithm (GA) approach has been developed. The proposed genetic algorithm uses a non-conventi...
VLSID
1996
IEEE
13 years 9 months ago
1996
IEEE
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
VLSID
1996
IEEE
13 years 9 months ago
1996
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process, and as a result several research efforts have been un...