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VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
11 years 11 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil
VLSID
2006
IEEE
145views VLSI» more  VLSID 2006»
11 years 11 months ago
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Sriniva...
VLSID
2006
IEEE
158views VLSI» more  VLSID 2006»
11 years 11 months ago
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
VLSID
2006
IEEE
143views VLSI» more  VLSID 2006»
11 years 11 months ago
Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems
This paper presents Frame Based Fair Multiprocessor Scheduler (FBFMS) which provides accurate real-time proportional fair scheduling for a set of dynamic tasks on a symmetric mult...
Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar
VLSID
2006
IEEE
95views VLSI» more  VLSID 2006»
11 years 11 months ago
Design of Embedded Systems with Novel Applications
Robert C. Lacovara, Dhadesugoor R. Vaman
VLSID
2006
IEEE
109views VLSI» more  VLSID 2006»
11 years 11 months ago
Carbon Nanotube Electronics
Ali Javey, Hongjie Dai
VLSID
2006
IEEE
87views VLSI» more  VLSID 2006»
11 years 11 months ago
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits
In this paper, for the first time, we analyze non-quasistatic (NQS) effects during single-event upsets (SEUs) in deep-submicron (DSM) MOS devices, using extensive 2D device, BSIM...
Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B...
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
11 years 11 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal
VLSID
2006
IEEE
94views VLSI» more  VLSID 2006»
11 years 11 months ago
On the Size and Generation of Minimal N-Detection Tests
The main result of this paper, proved as a theorem, is that a lower bound on the number of test vectors that detect each fault at least N times is N
Kalyana R. Kantipudi
VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
11 years 11 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran
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