Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm

We propose an algorithm for gate-delay fault diagnosis. It is based on the inject-and-evaluate paradigm [1], in which the fault site(s) are predicted through a series of injections and evaluations. Unlike the backtrace algorithm that predicts the fault site by tracing the syndrome at a faulty output back into the circuit, this approach mainly relies on the six-valued simulation. In such a forward approach, the accuracy is much higher because all the composite syndromes at all faulty outputs are considered simultaneously. We also analyze the effects of glitches and take them into account in our algorithm. As a result, the proposed approach is robust and applicable even when there are glitching outputs or when the delay size is relatively small. Experimental results show that the number of fault candidates produced by this approach is only 4.8 within 10 seconds of CPU time.

• Type: Conference
• Year: 2002
• Where: DFT
• Authors: Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang
• Keywords: DFT 2002, Fault Site, Faulty Outputs, Gate-delay Fault Diagnosis, VLSI