Compiler assisted dynamic management of registers for network processors

Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encountering long latency memory accesses and this way the parallelism and memory access can be overlapped. Context switches in the typical network processor architectures such as the IXP are designed to be very fast. However, the low overhead is partly achieved by leaving register management to programs, with minimal support from the hardware. The complexity of the multi-engine, multi-threaded environment makes manual register management a daunting task, which is better left to a compiler. However, a purely static analysis is unable to achieve full utilization of the register file due to conservative estimates of liveness. A register that is live across a context switch point must be considered live for the duration of all other threads, and so it must be assumed to be unavailable to other threads. In addition, a...

• Type: Conference
• Year: 2006
• Where: IPPS
• Authors: R. Collins, Fernando Alegre, Xiaotong Zhuang, Santosh Pande
• Keywords: Context Switch, Distributed And Parallel Computing, IPPS 2006, Network Processor, Threads Switch Context