A low power merge cell processor for real-time spike sorting in implantable neural prostheses

Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system with Model Result such strict constraints is implemented as an ASIC; however, the Training Recog- ^ Search Mining _ rapid progress in the field mandates a more flexible solution. In Set nition E Space V ng this paper we introduce a new general architecture, the Merge Framework, and its low power implementation for real-time spike sorting in cortical control applications, that offers a flexible and powerful programming model with near ASIC power efficiency. Model \

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: M. D. Linderman, T. H. Meng
• Keywords: Implantable Neural Decoders, ISCAS 2006, Low Power, Low Power Consumption