Hardware implementation of super minimum all digital FM demodulator

– We propose improvement of the new architecture of digital FM demodulator. This work enhances signal quality, system clock frequency, and superior than well known PLL technique today. No more multiplier, no more ROM or table, compact size, and very fast in transient or state response. Real implementation in Altera® APEX20K200 EBC652-1X PLD gives 348 logic elements and run up to 224.42 MHz.

• Type: Conference
• Year: 2006
• Where: ASPDAC
• Authors: Nursani Rahmatullah, Arif E. Nugroho
• Keywords: ASPDAC 2006, Clock Frequency, Digital Fm Demodulator, PLL Technique Today