Worst case execution time analysis for synthesized hardware

13 years 10 months ago

Download dtl.yonsei.ac.kr

- We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on some real-world applications show that our flow provides a tight upper bound of the execution time, and many useful hints to the designer.

Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-You

Real-time Traffic

ASPDAC 2006 | Execution Time | Performance Estimation Flow | Worst-case Execution Time |

claim paper

» Automatic Identification of Timing Anomalies for CycleAccurate WorstCase Execution Time An...

» MeasurementBased WorstCase Execution Time Analysis

» Worst Case Execution Time Analysis for Petri Net Models of Embedded Systems

» Modeling the Function Cache for WorstCase Execution Time Analysis

» Approximation of WorstCase Execution Time for Preemptive Multitasking Systems

» An Esterel processor with full preemption support and its worst case reaction time analysi...

» A Survey of WorstCase Execution Time Analysis for RealTime Java

» Worst case delay analysis for memory interference in multicore systems

Post Info
More Details (n/a)

Added	13 Jun 2010
Updated	13 Jun 2010
Type	Conference
Year	2006
Where	ASPDAC
Authors	Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-Young Chung, Kyu-Myung Choi

Comments (0)

Sciweavers

Worst case execution time analysis for synthesized hardware

ASPDAC 2006 | Execution Time | Performance Estimation Flow | Worst-case Execution Time |

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers