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ICCAD
1995
IEEE

Test register insertion with minimum hardware cost

12 years 1 months ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a scheme is implemented by test registers, for instance BILBOs and CBILBOs, which are inserted into the circuit structure at appropriate places. An algorithm is presented which is able to find the cost optimal placement of test registers for nearly all the ISCAS'89 sequential benchmark circuits, and a suboptimal solution with slightly higher costs is obtained for all the circuits within a few minutes of computing time. The algorithm can also be applied to the Minimum Feedback Vertex Set problem in partial scan design, and an optimal solution is found for all the benchmark circuits. The resulting self-testable circuits are analyzed. It is found that often CBILBOs lead to a minimum hardware overhead and also simplify test scheduling and test control.
Albrecht P. Stroele, Hans-Joachim Wunderlich
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where ICCAD
Authors Albrecht P. Stroele, Hans-Joachim Wunderlich
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